cy29940 2.5 v or 3.3 v, 200-mhz, 1:18 clock distribution buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07283 rev. *e revised may 11, 2011 2.5 v or 3.3 v, 200-mhz, 1:18 clock distribution buffer features 200-mhz clock support lvpecl or lvcmos/lvttl clock input lvcmos/lvttl compatible inputs 18 clock outputs: drive up to 36 clock lines 60 ps typical output-to-output skew dual or single supply operation: ? 3.3 v core and 3.3 v outputs ? 3.3 v core and 2.5 v outputs ? 2.5 v core and 2.5 v outputs pin compatible with mpc940l, mpc9109 available in commercial and industrial temperature 32-pin lqfp package description the cy29940 is a low-voltage 200-mhz clock distribution buffer with the capability to select either a differential lvpecl or a lvcmos/lvttl compatible input clock. the two clock sources can be used to provide for a test clock as well as the primary system clock. all other cont rol inputs are lvcmos/lvttl compatible. the eighteen outputs are 2.5 v or 3.3 v lvcmos/lvttl compatible and can drive 50 ? series or parallel terminated transmission lines. for series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. low output-to-output skews make the cy29940 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. block diagram pecl_clk pecl_clk# 0 1 tclk tclk_sel vddc 18 q0-q17 vdd cy29940 q0 q1 q2 vddc q3 q4 q5 vss q17 q16 q15 vss q14 q13 q12 vddc q6 q7 q8 vdd q9 q10 q11 vss vss vss tclk tclk_sel pecl_clk pecl_clk# vdd vddc 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 pin configuration [+] feedback
cy29940 document #: 38-07283 rev. *e page 2 of 10 pin description [1] pin name pwr i/o description 5 pecl_clk i, pu pecl input clock 6 pecl_clk# i, pd pecl input clock 3 tclk i, pd external reference/test clock input 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 q(17:0) vddc o clock outputs 4 tclk_sel i, pd clock select input. when low, pecl clock is selected and when high tclk is selected. 8, 16, 29 vddc 3.3 v or 2.5 v powe r supply for output clock buffers 7, 21 vdd 3.3 v or 2.5 v power supply 1, 2, 12, 17, 25 vss common ground note 1. pd = internal pull-down, pu = internal pull-up [+] feedback
cy29940 document #: 38-07283 rev. *e page 3 of 10 maximum ratings [2] maximum input voltage relative to v ss ............. v ss ? 0.3 v maximum input voltage relative to v dd ............. v dd + 0.3 v storage temperature ..... ............ ............... ?65 ? c to +150 ? c operating temperature............................... ?40 ? c to +85 ? c maximum esd protection .............................................. 2 kv maximum power supply................................................ 5.5 v maximum input current ............. .............. .............. .... 20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc parameters [2] v dd = 3.3 v 5% or 2.5 v 5%, v ddc = 3.3 v 5% or 2.5 v 5%, t a = ?40 ? c to +85 ? c parameter description conditions min typ max unit v il input low voltage v ss ?0.8v v ih input high voltage 2.0 ? v dd v i il input low current [3] ? ? ?200 a i ih input high current [3] ??200a v pp peak-to-peak input voltage pecl_clk 500 ? 1000 mv v cmr common mode range [4] pecl_clk v dd = 3.3 v v dd ? 1.4 ? v dd ? 0.6 v v dd = 2.5 v v dd ? 1.0 ? v dd ? 0.6 v v ol output low voltage [5, 6, 7] i ol = 20 ma ? ? 0.5 v v oh output high voltage [5, 6, 7] i oh = ?20 ma, v ddc = 3.3 v 2.4 ? ? v i oh = ?20 ma, v ddc = 2.5 v 1.8 ? ? v i ddq quiescent supply current ? 5 7 ma i dd dynamic supply current v dd = 3.3 v, outputs @ 150 mhz, cl = 15 pf ? 285 ? ma v dd = 3.3 v, outputs @ 200 mhz, cl = 15 pf ? 335 ? v dd = 2.5 v, outputs @ 150 mhz, cl = 15 pf ? 200 ? v dd = 2.5 v, outputs @ 200 mhz, cl = 15 pf ? 240 ? z out output impedance v dd = 3.3 v 8 12 16 ? v dd = 2.5 v 10 15 20 c in input capacitance ? 4 ? pf notes 2. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pi n during power-up. power supply sequencing is not required. 3. inputs have pull-up/pull-down resistors that effect input current. 4. the vcmr is the difference from the most positive side of the differential input signal. normal operation is obtained when th e ?high? input is within the vcmr range and the input lies within the vpp specification. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines 5. outputs driving 50 ?? transmission lines. 6. see figure 1 on page 5 and figure 2 on page 5 . 7. 50% input duty cycle. [+] feedback
cy29940 document #: 38-07283 rev. *e page 4 of 10 ac parameters [8] v dd = 3.3 v 5% or 2.5 v 5%, v ddc = 3.3 v 5% or 2.5 v 5%, t a = ?40 ? c to +85 ? c parameter description conditions min typ max unit f max input frequency ? ? ? 200 mhz t pd pecl_clk to q delay [9, 10, 11] ? 150 mhz v dd = 3.3 v, 85 ? ct phl 2.0 ? 3.2 ns t plh 2.1 ? 3.4 v dd = 3.3 v, 70 ? ct phl 1.9 ? 3.1 t plh 2.0 ? 3.2 v dd = 2.5 v, 85 ? ct phl 2.5 ? 5.2 t plh 2.6 ? 5 v dd = 2.5 v, 70 ? ct phl 2.5 ? 5 t plh 2.6 ? 5 t pd lvcmos to q delay [9, 10, 11] ? 150 mhz v dd = 3.3 v, 85 ? ct phl 1.9 ? 3 ns t plh 2.0 ? 3.2 v dd = 3.3 v, 70 ? ct phl 1.8 ? 2.9 t plh 1.8 ? 3.1 v dd = 2.5 v, 85 ? ct phl 2.5 ? 4 t plh 2.5 ? 4 v dd = 2.5 v, 70 ? ct phl 2.3 ? 3.8 t plh 2.3 ? 3.8 t j total jitter v dd = 3.3 v @ 150 mhz ? ? 10 ps foutdc output duty cycle [9, 10, 12] fclk < 134 mhz ? ? 55 % fclk > 134 mhz ? ? 60 t skew output-to-output skew [9, 10] v dd = 3.3 v ? 60 150 ps v dd = 2.5 v ? ? 200 t skew (pp) part-to-part skew [13] pecl, v ddc = 3.3 v ? ? 1.4 ns pecl, v ddc = 2.5 v ? ? 2.2 t skew (pp) part-to-part skew [13] tclk, v ddc = 3.3 v ? ? 1.2 ns tclk, v ddc = 2.5 v ? ? 1.7 t skew (pp) part to part skew [14] pecl_clk ? ? 850 ps tclk ? ? 750 t r /t f output clocks rise/fall time [9, 10] 0.7 v to 2.0 v, v ddc = 3.3 v 0.3 ? 1.1 ns 0.5 v to 1.8 v, v ddc = 2.5 v 0.3 ? 1.2 notes 8. parameters are guaranteed by design and characterization. not 100% tested in production. all parameters specified with loaded outputs. 9. outputs driving 50 ?? transmission lines. 10. see figure 1 on page 5 and figure 2 on page 5 . 11. parameters tested @ 150 mhz. 12. 50% input duty cycle. 13. across temperature and voltage ranges, includes output skew. 14. for a specific temperature and voltage, includes output skew. [+] feedback
cy29940 document #: 38-07283 rev. *e page 5 of 10 figure 1. lvcmos_clk cy29940 test reference for v cc = 3.3 v and v cc = 2.5 v figure 2. pecl_clk cy29940 test reference for v cc = 3.3 v and v cc = 2.5 v figure 3. propagation delay (tpd) test reference figure 4. lvcmos propagation delay (tpd) test reference pulse generator z = 50 ohm zo = 50 ohm vtt zo = 50 ohm vtt r t = 50 ohm r t = 50 ohm cy29940 dut differential pulse generator z = 50 ohm zo = 50 ohm zo = 50 ohm vtt r t = 50 ohm cy29940 dut zo = 50 ohm r t = 50 ohm vtt t pd pecl_clk pecl_clk v pp q v cmr vcc gnd vcc /2 t pd lvcmos_clk q vcc gnd vcc /2 vcc gnd vcc /2 [+] feedback
cy29940 document #: 38-07283 rev. *e page 6 of 10 figure 5. output duty cycle (foutdc) figure 6. output-to-output skew tsk(0) vcc gnd vcc /2 t p t0 dc = tp / t0 x 100% t sk(0) vcc gnd vcc /2 vcc gnd vcc /2 ordering information part number package type production flow pb-free cy29940axi 32-pin lqfp industrial, ?40 ? c to +85 ? c CY29940AXIT 32-pin lqfp ? tape and reel industrial, ?40 ? c to +85 ? c cy29940axc 32-pin lqfp commercial, 0 ? c to 70 ? c cy29940axct 32-pin lqfp ? tape and reel commercial, 0 ?? c to 70 ? c ordering code definitions t = tape and reel; blank = tube temperature range: x = c or i c = commercial; i = industrial pb-free package: a = 32-pin lqfp base part number company id: cy = cypress 29940 cy a x t x [+] feedback
cy29940 document #: 38-07283 rev. *e page 7 of 10 package drawing and dimensions figure 7. 32-pin tqfp 7 7 1.4 mm a32.14 51-85088 *c [+] feedback
cy29940 document #: 38-07283 rev. *e page 8 of 10 acronyms document conventions units of measure acronym description esd electrostatic discharge i/o input/output lqfp low-profile quad flat package lvcmos low voltage complementary metal oxide semiconductor lvpecl low-voltage positive emitter-coupled logic lvttl low-voltage transistor-transistor logic tqfp thin quad flat pack symbol unit of measure c degree celsius kv kilo volts mhz mega hertz a micro amperes ma milli amperes mm milli meter mv milli volts ns nano seconds ? ohms % percent pf pico farad ps pico seconds vvolts wwatts [+] feedback
cy29940 document #: 38-07283 rev. *e page 9 of 10 document history page document title: cy29940, 2.5 v or 3.3 v, 200-mhz, 1:18 clock distribution buffer document number: 38-07283 rev. ecn no. issue date orig. of change description of change ** 111094 02/01/02 brk new data sheet *a 116776 08/15/02 hwt incorporate results of final characterization using corporate methods, added output impedance on page 3 and added output duty cycle on page 4. add commercial temperature range in the ordering information on page 6. *b 122875 12/21/02 rbi add power up requirements to maximum rating information *c 448379 see ecn rgl add typical value for output-to-output skew add lead-free devices *d 2899304 03/25 /10 bash/kvm removed in active parts from ordering information. updated package diagram. *e 3254185 05/11/2011 cxq added ordering code definitions . added acronyms and units of measure . updated in new template. [+] feedback
document #: 38-07283 rev. *e revised may 11, 2011 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy29940 ? cypress semiconductor corporation, 2002-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback
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